The present invention relates to a method and an apparatus for judging whether or not a systematic defect is occurring in a preceding process of semiconductor device manufacture, and more specifically to a method and an apparatus for judging a systematic defect which method and apparatus are preferable for, especially in a state in which a plurality of layers are superposed on each other, identifying the layer contributing to the occurrence of the systematic defect attributable to circuit design and a circuit pattern within the layer.
Following advance in miniaturization of a circuit pattern of a semiconductor device, a method for manufacturing it has become increasingly sophisticated. Accordingly, there also arise changes in occurring defects. That is, while randomly occurring defects caused by, for example, dust or a foreign substance haven been conventionally dominant, following the miniaturization of the circuit pattern, highly design-dependent defects correlated with wire or element arrangements and defects caused by, for example, a shape of a specific layer or superposition of layers have increased.
These defects highly dependent on the circuit design are called systematic defects. They include: for example, resistance abnormality due to pattern shape variation attributable to a foundation step difference; and contact hole conduction failure due to unsatisfactory etching of a gate oxide film in a specific region.
The occurrence of the systematic defect can be prevented by changing design data of the shape or partially changing manufacturing condition in many cases. Thus, there have been increasing demands for a function of judging, from a defect detected by an inspection device, whether or not there is a defect (systematic defect) attributable to the circuit design.